Loading the an input port into one of the registers, multiplying by the other producing a 16-bit product in both makes a lot more sense.Įxcept for the multiply, this could be implemented fairly easily all of the arithmetic operations (add, subtract, compare) and logical operations (and, or, xor, not) can be performed by an ALU (Arithmetic/Logic Units), supported in Logisim. I didn't implement the concept of multiplying the "input buffer" by the "data cache" since the OP didn't specify any details about the cache - and I currently have the input buffer being read into either of the two registers. The high byte of the result goes into register d, and the low byte goes into register 1-d. The multiply instruction always multiplies register 0 by register 1. The way the multiply works is as follows: an 8x8 multiply gives a 16 bit result. It could be redone as branches instead by getting rid of the load immediate instructions: 0 1 b b a a a aĪ a a a is signed relative branch +- 8 bytes Using skips instead of branches allowed for a shorter address field. There are three kinds of branches: jump and call instructions, which take a full address an unconditional branch instruction that can branch backwards up to 16 bytes and conditional skip instructions that can skip up to 4 bytes ahead. Off, then either 4K bytes or 16 bytes can be addressed. I field specifies indexed addressing using the register R is the destination or source register (0 or 1) (or 3 bits provides access to 8 bytes of RAM) Load store from/to RAM (x = 0 is load, 1 is store)ġ1 bits of address provide direct access to 2K of RAM Or jump to 4K of program memory (or 5 bits provide P is reserved for a page bit (or could just be the highīit of address). Jump or call instruction (x = 0 is jump, 1 is call) Load immediate to register r (0 or 1) signed value nnnnĪ a a a a a a a (2nd byte only for extended format) I i = # of bytes to skip typically 1 or 2, latter for Used for branching back at end of a short loop after a skip (s=0 means s field is 0, not that the register is 0)ġ100 inp1 s = 0 input to reg d from input port 1ġ100 inp2 s = 1 input to reg d from input port 2ġ101 out1 s = 0 output from reg d to output port 1ġ101 out2 s = 1 output from reg d to output port 2ġ110 mul d/s = s * d (high byte of result into d, low byte into 1-d)īrn - unconditional branch negative -n bytes (up to -16), I left in the long formats, because if one includes them, I think this would make a reasonable 8-bit computer (even though it can only address 4K bytes).Īlthough I favor memory-mapped I/O over input/output instructions, I provided two of each to satisfy the spec. All instructions are one byte except for the four requiring full addresses (optional, as described earlier, leave off this 2nd byte for 4 bit addressing). So the following is an instruction set based on the specification of two registers. However, if you leave off this extra byte, then my instruction format allows for 5 bits (not just 4) of program address, and up to 4 bits of RAM addressing. So I came up with a scheme using a two-byte instruction for jumps, calls, load and stores which would give you a 12 bit address or 4096 location. For a real computer, you definitively would want more than 4 bits of program address since 4 bits only allows 16 instructions.
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